Architectural conception and network processor development which provide intelectual data processing.
State registration – 0109U002268
Head - Simonenko Valeriy.P
A set of methods for pipelined computer system synthesis is developed. The methods are based on mapping the spaced synchronous dataflow graphs (SSDFG) into the system structure and its schedule. The input data of the methods are initial SSDFG, given period of the algorithm implementation, and optimization criterium. The developed methods provide minimising the clock period as well as processor unit, register, multiplexor number, interprocessor communications, memory volume, energy consumption minimizations. A set of methods for synthesis of the pipelined computer systems for the field programable gate array (FPGA) is developed. It includes method based on the VHDL language, method of mapping the iterative algorithms with the control operators. The resulting computer structure is described by VHDL and is a project which is ready to be configured in FPGA or implemented in ASIC. Due to the fact that this project is built without the very structure synthesis, the project optimization process is straight and has less complexity. The method of SSDFG retiming is proposed which is directed and has less complexity comparing to the usual retiming. The method description level provides its implementation in some computer aided design frameworks.
The methods are checked by the design of a set of application specific processors for the digital signal processing and the linear algebra problem solving, which are implemented in FPGA. The parameters of the resulting processes are equal to or supersede the parameters of the best known processors. It was found out that the network processors based on the configurable computers have much less energy consumption and increased speed comparing to the microprocessor systems. Theu can be configured by the means of proposed methods. A method for the static schedule of a set of tasks in the network processor system with the resource constraints is proposed which minimizes the common computation time due do the data dependence graph processing. The method provides the effective schedule finding in real time.
A set of intelectual property cores (IP cores) for the configurable network processor building is developed. It contains the media acces controller core, Reed-Solomon decoder, GZIP file decompressor. i8051 microcontroller core is developed which has increased speed up to 100 mln. instructions per second. An experimental network processor based on Xilinx XCV-4SX35 FPGA was designed and probed.