Методы и средства Methods and means of increasing the efficiency of solving problems on the basis of reconfigurable computing facilities on the FPGAэффективности решения задач на основе перестраиваемых вычислительных средств на ПЛИС

Спеціалізований суперскалярний процесор з множиною реконфігурованих обчислювальних блоків під керівництвом обмеженої схеми потоку даних

1. State registration number, registration number at the university.
№ of the State registration number 0114U000547, registration number at the university 2711f.
2. Scientific supervisor (scientific degree, rank). Lutsky Georgy, doctor of technical science, professor.
3. The essence of the development, the main results.

Developed theoretical foundations for creation of multilayered FPGA-based matrix structure managed by restricted dataflow model. Created and investigated models of multilayered FPGA-based matrix structure managed by restricted dataflow. Developed new concept of building problem-oriented processor, implementation of which is based on using multiple FPGA. Developed new methodology of creation of multilayered FPGA matrix managed by restricted dataflow model. Depending on task which is needed to be executed, multilayered FPGA-based matrix structure can contain hundreds of thousands reconfigurable logical elements interconnected with a communication network and form specialized pipeline processor or superscalar processor with multiple specialized computation elements managed by restricted dataflow model. The specialized computation elements can be programmed on any complex mathematical operations in a contrast to restricted number of RISC-operations that can be executed by functional elements of processor core with traditional superscalar architecture. Centralized management platform based on a standard PC is used for programming and reconfigurations of FPGA-based matrix structure. Investigated hardware that implements restricted dataflow model in modern superscalar microprocessors. Developed a configuration library of computational modules for processor with pipeline architecture and for microarchitecture of processor core with superscalar architecture. Methodology of creation of multilayered FPGA matrix was tested on development of multichannel FIR-filters each of which targets its own narrow channel.

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