Development of theoretical basics, methods and tools for design of modern high speed computer systems in Grid and Cloud systems

Експериментальний зразок конфігурованого комп'ютера, підключеного до HP Blade server C3000

1. State registration number of the theme  0112U001585, NTUU "KPI" - 2502-f.
2. Supervisor prof. Simonenko Valeriy.P.
3. The main results.

A new architectural concept of parallel computing in GRID systems and cloud environment is proposed, which uses FPGA as a high-performance heterogeneous computing resource. FPGA is used as heterogeneous programmable operating unit for processing data streams, allowing for achievement of optimized performance-related energy consumption. The concept simplifies programming the computational problems for these systems. New approaches to computation scheduling in heterogeneous GRID systems are developed, that allow for optimizing the workload of computing resources, and effectively carry out their monitoring. A new method of resynchronization of synchronous dataflow graphs is proposed, that provides design of pipelined datapaths for FPGAs, which have minimized costs and optimized performance. The CAD tool of parallel computing systems described in VHDL is designed which is based on this method. The tool is implemented as an application in the cloud environment. The client side of the experimental CAD tool is installed on a Web-browser, and the server side is installed in the HP Blade server C3000, which is placed in NTUU "KPI".

The divider, square root, IIR filter core generator is designed, which generates the pipelined IP cores with excellent parameters of speed and hardware volume. The IIR filters are multiplier free, and their structures are found using the filter structure ontology and applied knowledge base. The IP core generators are intended for installing in a cloud environment, or in Web-server. The generated digital filters have minimum hardware costs and maximum sample rate that achieves to 400 MHz.

Developed CAD tools helped to design a number of IP cores such as Ethernet controller, Reed-Solomon decoder, pipelined FFT processors, 2-D DCT processors, microprocessor ARMv.3 core, i8051 microcontroller core, which has a performance of 100 mln. instructions per second.

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