Development of theoretical foundation for creation of high-performance computer systems with run-time parallelization of computational processes

Developed theoretical foundations for construction of superscalar RISC-microprocessor kernel architecture with extended properties of parallelism exposure at the level of commands. Parallelism improvements at the level of commands was achieved by organization of simultaneous decoding on RISC-operations of 32 byte command window of the processed threads and simultaneous treatment of up to four threads of instructions from a set of x86-64. Decoding of command windows, in relation to the processed threads, takes place by turns. Decoding of command windows, in relation to the commands of a processed thread, takes place with the prognosis of their branching and extraordinary execution start. In the developed architecture of processor kernel the decentralized way of control and management of the processes of command execution is applied in a conveyer, which is distributed on all conveyer segments. At the completion of one of the processed threads of instructions, instead of it the service thread of instructions is started with the virtual number of process 0. It dispatches other thread of instructions for execution, choosing between the threads prepared to execution. It also reloads part of register memory of missing page handling of virtual application memory, and also parts of all caches and buffers of TLB of processor kernel, which are related to handling of virtual number of the requested process (from 1 to 4).

Developed new approach of practical decision process of tasks of dynamic planning for the parallel systems, built on the basis of processors with classic architecture, which is based on the use of thread model of calculations. Essence of the new approach was investigated on the examples of realization of algorithms of some popular numeral methods.