часткова реконфігурація

Methods and means of increasing the efficiency of solving problems on the basis of reconfigurable computing facilities on the FPGA

Спеціалізований суперскалярний процесор з множиною реконфігурованих обчислювальних блоків під керівництвом обмеженої схеми потоку даних

Developed theoretical foundations for creation of multilayered FPGA-based matrix structure managed by restricted dataflow model. Created and investigated models of multilayered FPGA-based matrix structure managed by restricted dataflow. Developed new concept of building problem-oriented processor, implementation of which is based on using multiple FPGA. Developed new methodology of creation of multilayered FPGA matrix managed by restricted dataflow model.