Architectural conception and network processor development which provide intelectual data processing.
A set of methods for pipelined computer system synthesis is developed. The methods are based on mapping the spaced synchronous dataflow graphs (SSDFG) into the system structure and its schedule. The input data of the methods are initial SSDFG, given period of the algorithm implementation, and optimization criterium. The developed methods provide minimising the clock period as well as processor unit, register, multiplexor number, interprocessor communications, memory volume, energy consumption minimizations.