ip core

Computer aided design tool development and their use for the high-speed vision processor design

Computer aided design tool development  and their use for the high-speed vision processor design

The vision system for the high dynamic range (HDR) video signals is developed. The system performs the HDR image compression to the signal with dynamic range of 48 dB without loss of sharpness in the light and dark areas and no artifacts, and has moderate hardware costs when it is implemented in FPGA. The Retinex compression algorithm based on the bilateral function is considered. A simplified HDR compression algorithm is proposed, that uses the intelligent image analysis of local characteristics instead of the bilateral function .