Суперскалярний RISC-мікропроцесор

Development of theoretical foundation for creation of high-performance computer systems with run-time parallelization of computational processes

Developed theoretical foundations for construction of superscalar RISC-microprocessor kernel architecture with extended properties of parallelism exposure at the level of commands. Parallelism improvements at the level of commands was achieved by organization of simultaneous decoding on RISC-operations of 32 byte command window of the processed threads and simultaneous treatment of up to four threads of instructions from a set of x86-64. Decoding of command windows, in relation to the processed threads, takes place by turns.