Development of theoretical basics, methods and tools for design of modern high speed computer systems in Grid and Cloud systems

Експериментальний зразок конфігурованого комп'ютера, підключеного до HP Blade server C3000

A new architectural concept of parallel computing in GRID systems and cloud environment is proposed, which uses FPGA as a high-performance heterogeneous computing resource. FPGA is used as heterogeneous programmable operating unit for processing data streams, allowing for achievement of optimized performance-related energy consumption. The concept simplifies programming the computational problems for these systems.

Terahertz broadband telecommunications system radio access with Gigabit bandwidth


The principles and hardware / software solutions to build a telecommunication system broadband Internet access with Gigabit bandwidth in the frequency range 128-134 GHz to solve congestion frequency bands used today, a substantial increase in the data rate of wireless radio access systems, and the creation of ultra high radio relay lines of the new generation.

Hierarchical Internet-oriented microserver systems for remote experimental data asquisition and processing

Hardware-software complex for development of distributed informational-measurement microcontroller systems with microserver Internet access based on hierarchical structures of multilevel measurement systems was developed. New structural and technical solutions for multilevel data acquisition systems were suggested. The system is built as a two-level microserver Ethernet-network of virtual measurement modules. Test samples of basic hardware/software tools were designed.

Architectural conception and network processor development which provide intelectual data processing.

A set of methods for pipelined computer system synthesis is developed. The methods are based on mapping the spaced synchronous dataflow graphs (SSDFG) into the system structure and its schedule. The input data of the methods are initial SSDFG, given period of the algorithm implementation, and optimization criterium. The developed methods provide minimising the clock period as well as processor unit, register, multiplexor number, interprocessor communications, memory volume, energy consumption minimizations.